This article explains in detail why two-FF synchronizers can help prevent metastability from propagating and resolve CDC issues in digital IC design.
As explained in this article, the main problem with Clock Domain Crossing (CDC) is metastability due to setup or hold time violations of asynchronous crossing signals when capturing by the destination clock domain, in which the metastable state can propagate throughout the design causing data loss and even chip malfunction. Metastability in CDC design is not preventable, but synchronizers can be employed to avoid the propagation of the metastable state; hence, prevent system failures.
How can two-FF synchronizers prevent metastability from propagating?
As explained in this article and also shown in the waveform above, when the first flip-flop (FF) data input violates the setup or hold time requirements, the output A/B becomes metastable. However, after an unpredictable delay (Tco), the FF output would settle to a stable logic level. Read here to understand FF metastability.
This is where the second FF comes in and prevent metastability from propagating throughout the design. As the metastable state would settle to a stable state after Tco, when captured by the second FF at the next rising edge of the clock, the Q1 output or D2 input data is likely to be already stable and there is likely no setup or hold time violation. Thus, FF2 can successfully store the stable logic level of Q1/D1 without metastability. In other words, the metastable state can be resolved by the second FF and the output of FF2 can be safely used by the next logic block.
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| Three-FF synchronizer |
The probability of design failures due to metastability is modeled by the Mean Time Between Failures (MTBF) parameter. You can read more about MTBF here.
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